1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for generating a polishing process endpoint signal using scatterometry.
2. Description of the Related Art
Chemical mechanical polishing (CMP) is a widely used means of planarizing silicon dioxide as well as other types of layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, the surface of the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to control and minimize within-wafer topography variations. For example, in one embodiment, to minimize spatial variations in downstream photolithography and etch processes, it is necessary for the thicknesses of the process layer (e.g., silicon dioxide) formed an a wafer to be as uniform as possible (i.e., it is desirable for the surface of the process layer to be as planar as possible).
Those skilled in the art will appreciate that a variety of factors may contribute to producing variations across the post-polish surface of a process layer. For example, variations in the surface of the wafer may be attributed to drift of the chemical mechanical polishing device. Typically, a chemical mechanical polishing device is optimized for a particular process, but because of chemical and mechanical changes to the polishing pad during polishing, degradation of process consumables, and other processing factors, the chemical mechanical polishing process may drift from its optimized state.
Typically, the operating recipes for polishing tools are determined during the process characterization stage, because no in-line techniques are readily available for determining the planarity of the polished surface. Based on design factors, such as the topology of the underlying features and the thickness of the layer to be polished, polishing targets are generated to help ensure that the polishing time is sufficient to planarize the process layer being polished without overpolishing and damaging the underlying structures. FIG. 1A illustrates a cross-section of an exemplary semiconductor device 100 that is subjected to a planarization process. The semiconductor device 100 includes a plurality of interconnect structures 110 (e.g., aluminum stacks) formed on a previous interlayer dielectric (ILD) layer 120 (e.g., silicon dioxide formed using tetraethoxysilane (TEOS) or fluorine doped tetraethoxysilane (F-TEOS)). For clarity and ease of illustration, not all features of the interconnect structures 110 are shown. Typically, an aluminum interconnect stack includes a titanium layer over the ILD layer 120, a titanium nitride layer, an aluminum layer, a second titanium nitride layer, and a silicon oxide hard mask layer. A second ILD layer 130 is formed over the interconnect structures 110. The ILD layer 130 is polished to produce an approximately planar surface 135 of the ILD layer 130, as shown in FIG. 1B. If the ILD layer 130 is underpolished, the surface 135 will not be as planar as desired, which may interfere with formation of features in subsequent layers. If the ILD layer 130 is overpolished, the insulative capability of the ILD layer 130 may be reduced.
Other exemplary process layers that are commonly subjected to polishing processes are ILD layers formed over transistor gate electrode stacks or silicon dioxide layers used to form shallow trench isolation (STI) structures formed in a substrate between active devices (e.g., transistors) in the semiconductor device. Overpolishing or underpolishing may also cause problems with these structures.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a method for polishing wafers. The method includes polishing a process layer formed on a wafer, the process layer overlying a grating structure; illuminating at least a portion of the process layer and the grating structure; measuring light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile; comparing the measured reflection profile to a target reflection profile having an acceptable degree of planarity; and terminating the polishing of the process layer based on the comparison of the measured reflection profile and the target reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to measure a wafer having a grating structure and a process layer formed over the grating structure after initiation of a polishing process. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the process layer overlying the grating structure. The detector is adapted to measure light reflected from the illuminated portion of the process layer and the grating structure to generate a reflection profile. The data processing unit is adapted to compare the measured reflection profile to a target reflection profile having an acceptable degree of planarity and generate an endpoint signal based on the comparison of the measured reflection profile and the target reflection profile.